1. Technical Field
The present disclosure relates to a solid-state image capturing device.
2. Description of the Related Art
Recently, a CMOS image sensor, which has excellent features of high speed and high sensitivity, is used for image capturing devices of large numbers of single-lens reflex digital cameras and fixed-lens digital cameras. The CMOS image sensor includes: a pixel portion in which pixels performing photoelectric conversion are arranged two-dimensionally; a column ADC (Analog-to-Digital Converter) circuit that performs digital conversion for pixel signals read out from the pixel portion; and a digital balancer that averages the digitized pixel signals in response to a drive mode. As the drive mode, there are: a full scan mode for use in capturing a static image; and a mixture mode for capturing a monitor image for use in a live view (electronic finder) and the like. In the full scan mode, the pixel signals are output independently of one another without being averaged in the digital balancer, and in the mixture mode, a plurality of the pixel signals are added to one another in the digital balancer, and are then output. Note that a number of base units of the column ADC is equal to or more than a number of columns
In general, when a number of the pixels which compose the pixel portion is increased, resolution of a captured image is enhanced. Accordingly, a number of pixels of the image sensor has been as huge as several ten millions. Moreover, a quantity of light input to the pixel portion is increased as an area of the pixel portion is larger. Accordingly, as the pixel portion has a larger area, the pixel portion is more suitable for enhancement of image quality. Therefore, a demand for a camera using a sensor with a large area of the pixel portion has been increasing. For example, in a camera with a format of a 35 mm full size, the area of the pixel portion is 36 mm×24 mm. If the huge number of pixels are arranged on such a large area, then it takes a longer time to capture an image since a load on readout lines is increased and a number of signals to be read out is increased. Such a problem as described above has occurred.
For this problem, FIG. 1 of Unexamined Japanese Patent Publication No. 2010-98516 illustrates enhancement of speed, which is brought by division of vertical signal lines on a center of the pixel portion. Specifically, in a configuration disclosed in Unexamined Japanese Patent Publication No. 2010-98516, on an upper half and lower half of the pixel portion, the pixel signals are read out simultaneously by using two vertical signal lines (one vertical signal line before the division), whereby a load on each of the vertical signal lines is reduced. In such a way, in the configuration concerned, the readout can be accelerated. Note that the number of base units of the column ADC is equal to or more than double the number of columns
Moreover, FIG. 5 of Unexamined Japanese Patent Publication No. 2005-347932 illustrates a configuration of enhancing such a readout speed by disposing two vertical signal lines in each column in parallel. Specifically, in the configuration disclosed in Unexamined Japanese Patent Publication No. 2005-347932, the readout speed can be enhanced by simultaneously reading out signals in odd-number rows and even-number rows by using two vertical signal lines. Note that the number of base units of the column ADC is equal to or more than double the number of columns